26 search results - page 5 / 6 » Loop Optimization using Hierarchical Compilation and Kernel ... |
ISHPC
2003
Springer
13 years 10 months ago
2003
Springer
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
CGO
2010
IEEE
14 years 6 days ago
2010
IEEE
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
IPPS
2009
IEEE
13 years 12 months ago
2009
IEEE
Stencil computation (SC) is of critical importance for broad scientific and engineering applications. However, it is a challenge to optimize complex, highorder SC on emerging clus...
CGO
2006
IEEE
13 years 11 months ago
2006
IEEE
Most programs are repetitive, where similar behavior can be seen at different execution times. Algorithms have been proposed that automatically group similar portions of a program...