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» Loop Scheduling and Partitions for Hiding Memory Latencies
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PLDI
1995
ACM
13 years 8 months ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 4 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
ISCAPDCS
2004
13 years 6 months ago
FG: A Framework Generator for Hiding Latency in Parallel Programs Running on Clusters
FG is a programming environment for asynchronous programs that run on clusters and fit into a pipeline framework. It enables the programmer to write a series of synchronous functi...
Thomas H. Cormen, Elena Riccio Davidson
DATE
2008
IEEE
107views Hardware» more  DATE 2008»
13 years 11 months ago
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints
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Chun Jason Xue, Edwin Hsing-Mean Sha, Zili Shao, M...
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
13 years 11 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...