Sciweavers

16 search results - page 1 / 4
» Low Latency Recovery from Transient Faults for Pipelined Pro...
Sort
View
DSD
2010
IEEE
149views Hardware» more  DSD 2010»
13 years 2 months ago
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures
Abstract--Recent technology trends have made radiationinduced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace i...
Marcus Jeitler, Jakob Lechner
ISCA
2003
IEEE
136views Hardware» more  ISCA 2003»
13 years 9 months ago
Transient-Fault Recovery for Chip Multiprocessors
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz,...
DATE
2008
IEEE
75views Hardware» more  DATE 2008»
13 years 11 months ago
A low-cost concurrent error detection technique for processor control logic
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srin...
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
13 years 10 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh
HPCA
2002
IEEE
14 years 4 months ago
Loose Loops Sink Chips
This paper explores the concept of micro-architectural loops and discusses their impact on processor pipelines. In particular, we establish the relationship between loose loops an...
Eric Borch, Eric Tune, Srilatha Manne, Joel S. Eme...