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» Low Power Monolithic 3D IC Design of Asynchronous AES Core
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VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
13 years 8 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad
AES
2005
Springer
137views Cryptology» more  AES 2005»
13 years 4 months ago
Design of a multimedia processor based on metrics computation
Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-...
Nader Ben Amor, Yannick Le Moullec, Jean-Philippe ...