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» Low complexity LDPC code decoders for next generation standa...
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ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
13 years 9 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...
AAECC
2006
Springer
122views Algorithms» more  AAECC 2006»
13 years 9 months ago
Low-Floor Tanner Codes Via Hamming-Node or RSCC-Node Doping
We study the design of structured Tanner codes with low error-rate floors on the AWGN channel. The design technique involves the "doping" of standard LDPC (proto-)graphs,...
Shadi Abu-Surra, Gianluigi Liva, William E. Ryan
VLSISP
2010
140views more  VLSISP 2010»
13 years 3 months ago
A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders
A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The proposed method signific...
Tinoosh Mohsenin, Bevan M. Baas
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Design methodology for IRA codes
Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of Low-...
Frank Kienle, Norbert Wehn
ICASSP
2011
IEEE
12 years 9 months ago
Efficient iterative receiver for bit-Interleaved Coded Modulation according to the DVB-T2 standard
Bit-Interleaved Coded Modulation (BICM) offers a significant improvement in error correcting performance for coded modulations over fading channels compared to the previously exis...
Meng Li, Charbel Abdel Nour, Christophe Jég...