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ISCAS
1999
IEEE
134views Hardware» more  ISCAS 1999»
13 years 8 months ago
Low power DCT implementation approach for VLSI DSP processors
This paper presents an algorithm for the low power implementation of the Discrete Cosine Transform on Single multiplier CMOS DSPs. The algorithm reduces power by a combination of ...
S. Masupe, T. Arslan
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
13 years 8 months ago
Multi-objective design strategy for high-level low power design of DSP systems
High-level power design presents a complex, multiobjective problem that involves the simultaneous optimisation of competing criteria such as speed, area and power. It is difficult...
Mark S. Bright, Tughrul Arslan
IPPS
1998
IEEE
13 years 7 months ago
Evaluation of a Low-Power Reconfigurable DSP Architecture
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an archit...
Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marl...
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
13 years 9 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
13 years 8 months ago
Security-Driven Exploration of Cryptography in DSP Cores
With the popularity of wireless communication devices a new important dimension of embedded systems design has arisen, that of security. This paper presents for the first time des...
Catherine H. Gebotys