173 search results - page 4 / 35 » Low power and low voltage CMOS digital circuit techniques |
DATE
2006
IEEE
13 years 12 months ago
2006
IEEE
This paper reports a high speed and low power consumption direct–indirect bootstrapped full–swing CMOS inverter driver circuit (bfi–driver). The simulation results, based o...
IEICET
2008
13 years 5 months ago
2008
ISLPED
2003
ACM
13 years 11 months ago
2003
ACM
The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative ...
PATMOS
2005
Springer
13 years 11 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
VLSID
2003
IEEE
14 years 6 months ago
2003
IEEE
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...