67 search results - page 13 / 14 » Low power architecture for high speed packet classification |
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
CDES
2006
13 years 6 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
SEUS
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract— This paper presents SW synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore...
AAAI
2006
13 years 6 months ago
2006
Intrusion attempts due to self-propagating code are becoming an increasingly urgent problem, in part due to the homogeneous makeup of the internet. Recent advances in anomalybased...
TECS
2008
13 years 4 months ago
2008
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...