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    ISLPED
    2009
    ACM
    168views Hardware» more  ISLPED 2009»
    Low power circuit design based on heterojunction tunneling transistors (HETTs)
    13 years 10 months ago
    Low power circuit design based on heterojunction tunneling transistors (HETTs)
    Download  www.eecs.umich.edu
    The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
    Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
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    DAC
    2007
    ACM
    196views Computer Architecture» more  DAC 2007»
    Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors
    14 years 5 months ago
    Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors
    Download  post.queensu.ca
    Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultralow-power designs may even permit embedded systems...
    Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert ...
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    ISCAS
    2006
    IEEE
    119views Hardware» more  ISCAS 2006»
    Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
    13 years 10 months ago
    Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
    Download  www.cs.bris.ac.uk
    In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
    Saraju P. Mohanty, Elias Kougianos, Ramakrishna Ve...
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    ASPDAC
    2011
    ACM
    167views Hardware» more  ASPDAC 2011»
    Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic lig
    12 years 8 months ago
    Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic lig
    Download  web.ics.purdue.edu
    - In low temperature polycrystalline silicon (LTPS) based display technologies, the electrical parameter variations in thin film transistors (TFTs) caused by random grain boundarie...
    Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaus...
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    DATE
    2005
    IEEE
    154views Hardware» more  DATE 2005»
    Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
    13 years 10 months ago
    Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
    Download  infoscience.epfl.ch
    We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
    Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...
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