97 search results - page 2 / 20 » Low power network processor design using clock gating |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
HPCA
2003
IEEE
14 years 5 months ago
2003
IEEE
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
FPL
2010
Springer
13 years 3 months ago
2010
Springer
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the to...
ISLPED
1995
ACM
13 years 8 months ago
1995
ACM
This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...