42 search results - page 9 / 9 » Low-Power, High-Speed CMOS VLSI Design |
ISLPED
1997
ACM
13 years 9 months ago
1997
ACM
In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...