Sciweavers

129 search results - page 1 / 26
» Lower bounds on power dissipation for DSP algorithms
Sort
View
ICCAD
1994
IEEE
61views Hardware» more  ICCAD 1994»
13 years 7 months ago
Simultaneous driver and wire sizing for performance and power optimization
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
Jason Cong, Cheng-Kok Koh
TVLSI
1998
81views more  TVLSI 1998»
13 years 3 months ago
Maximum power estimation for CMOS circuits using deterministic and statistical approaches
— Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efï...
Chuan-Yu Wang, Kaushik Roy
ISCAS
1995
IEEE
107views Hardware» more  ISCAS 1995»
13 years 7 months ago
Power Dissipation in Deep Submicron CMOS Digital Circuits
— This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley S...
R. X. Gu, Mohamed I. Elmasry
ISLPED
1996
ACM
110views Hardware» more  ISLPED 1996»
13 years 7 months ago
Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques
In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power ba...
Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang