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ISCA
1994
IEEE
98views Hardware» more  ISCA 1994»
13 years 9 months ago
METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks
Frederic T. Chong, Henry Minsky, André DeHo...
INFOCOM
1999
IEEE
13 years 9 months ago
High Performance IP Routing Table Lookup using CPU Caching
Wire-speed IP (Internet Protocol) routers require very fast routing table lookup for incoming IP packets. The routing table lookup operation is time consuming because the part of ...
Tzi-cker Chiueh, Prashant Pradhan
TPDS
2002
105views more  TPDS 2002»
13 years 4 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
13 years 11 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
BNT
1997
13 years 6 months ago
Tag-switching architecture: overview
Tag switching is a way to combine the label-swapping forwarding paradigm with network layer routing. This has several advantages. Tags can have a wide spectrum of forwarding granu...
Yakov Rekhter