44 search results - page 1 / 9 » MOS VLSI circuit simulation by hardware accelerator using se... |
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
ICCAD
1991
IEEE
13 years 8 months ago
1991
IEEE
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
CORR
2010
Springer
13 years 4 months ago
2010
Springer
The Glottal Source is an important component of voice as it can be considered as the excitation signal to the voice apparatus. Nowadays, new techniques of speech processing such a...
ICCD
1993
IEEE
13 years 8 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
We present an algorithm to automatically design posynomial models for parameters of the MOS transistors using simulation data. These models improve the accuracy of the Geometric P...