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» Making DRAM Refresh Predictable
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ECRTS
2010
IEEE
13 years 4 months ago
Making DRAM Refresh Predictable
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...
Balasubramanya Bhat, Frank Mueller
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
11 years 6 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
ESTIMEDIA
2007
Springer
13 years 9 months ago
Network Calculus Applied to Verification of Memory Access Performance in SoCs
SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes t...
Tomas Henriksson, Pieter van der Wolf, Axel Jantsc...
USS
2008
13 years 6 months ago
Lest We Remember: Cold Boot Attacks on Encryption Keys
Contrary to popular assumption, DRAMs used in most modern computers retain their contents for several seconds after power is lost, even at room temperature and even if removed fro...
J. Alex Halderman, Seth D. Schoen, Nadia Heninger,...
SIGGRAPH
2010
ACM
13 years 8 months ago
Apparent display resolution enhancement for moving images
Limited spatial resolution of current displays makes the depiction of very fine spatial details difficult. This work proposes a novel method applied to moving images that takes ...
Piotr Didyk, Elmar Eisemann, Tobias Ritschel, Karo...