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» Managing on-chip inductive effects
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ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect
Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper int...
Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud
DSD
2006
IEEE
120views Hardware» more  DSD 2006»
13 years 11 months ago
Adaptive Power Management for the On-Chip Communication Network
— An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this regi...
Guang Liang, Axel Jantsch
MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
13 years 11 months ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
TVLSI
2002
78views more  TVLSI 2002»
13 years 4 months ago
Managing on-chip inductive effects
With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence o...
Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq ...
CONTEXT
2007
Springer
13 years 11 months ago
Risk Context Effects in Inductive Reasoning: An Experimental and Computational Modeling Study
Mechanisms that underlie the inductive reasoning process in risk contexts are investigated. Experimental results indicate that people rate the same inductive reasoning argument dif...
Kayo Sakamoto, Masanori Nakagawa