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ICCAD
2005
IEEE
131views Hardware» more  ICCAD 2005»
14 years 3 months ago
Code restructuring for improving cache performance of MPSoCs
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
Guilin Chen, Mahmut T. Kandemir
EURONGI
2006
Springer
13 years 9 months ago
Job Scheduling for Maximal Throughput in Autonomic Computing Systems
Abstract. Autonomic computing networks manage multiple tasks over a distributed network of resources. In this paper, we view an autonomic computing system as a network of queues, w...
Kevin Ross, Nicholas Bambos
IPPS
2007
IEEE
14 years 13 days ago
Knowledge and Cache Conscious Algorithm Design and Systems Support for Data Mining Algorithms
The knowledge discovery process is interactive in nature and therefore minimizing query response time is imperative. The compute and memory intensive nature of data mining algorit...
Amol Ghoting, Gregory Buehrer, Matthew Goyder, Shi...
DATE
2005
IEEE
171views Hardware» more  DATE 2005»
13 years 11 months ago
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems
As compared to a large spectrum of performance optimizations, relatively little effort has been dedicated to optimize other aspects of embedded applications such as memory space r...
Ozcan Ozturk, Hendra Saputra, Mahmut T. Kandemir, ...
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
13 years 11 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron