6 search results - page 1 / 2 » Mechanisms for bounding vulnerabilities of processor structu... |
ISCA
2007
IEEE
13 years 10 months ago
2007
IEEE
Concern for the increasing susceptibility of processor structures to transient errors has led to several recent research efforts that propose architectural techniques to enhance r...
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering ...
ASPLOS
2006
ACM
13 years 8 months ago
2006
ACM
Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around t...
ASPLOS
2008
ACM
13 years 6 months ago
2008
ACM
The C programming language is at least as well known for its absence of spatial memory safety guarantees (i.e., lack of bounds checking) as it is for its high performance. C'...
ICPP
2008
IEEE
13 years 11 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...