98 search results - page 2 / 20 » Memory Access Scheduling Schemes for Systems with Multi-Core... |
DATE
2007
IEEE
14 years 9 days ago
2007
IEEE
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
CONCURRENCY
2006
13 years 6 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
DAC
2004
ACM
14 years 7 months ago
2004
ACM
Memory-related activity is one of the major sources of energy consumption in embedded systems. Many types of memories used in embedded systems allow multiple operating modes (e.g....
FPL
2007
Springer
14 years 4 days ago
2007
Springer
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
ISCA
2000
IEEE
13 years 10 months ago
2000
IEEE
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...