117 search results - page 1 / 24 » Memory Access Schemes for Configurable Processors |
FPL
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. This work discusses the Memory Architecture for Reconfigurable Computers (MARC), a scalable, device-independent memory interface that supports both irregular (via configu...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
We propose an interleaved memory organization supporting multi-pattern parallel accesses in twodimensional (2D) addressing space. Our proposal targets computing systems with high ...
ISCA
1999
IEEE
13 years 9 months ago
1999
IEEE
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
ICPP
2008
IEEE
13 years 11 months ago
2008
IEEE
On systems with multi-core processors, the memory access scheduling scheme plays an important role not only in utilizing the limited memory bandwidth but also in balancing the pro...
DSD
2002
IEEE
13 years 9 months ago
2002
IEEE
A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done ...