236 search results - page 1 / 48 » Memory Bank Predictors |
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— Recent research has shown that forwarding speculative data to other processors before it is requested can improve the performance of multiprocessor systems. The most re...
ICCD
2002
IEEE
14 years 1 months ago
2002
IEEE
We introduce Branch Predictor Prediction (BPP) as a power-aware branch prediction technique for high performance processors. Our predictor reduces branch prediction power dissipat...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Main memories can consume a large percentage of overall energy in many data-intensive embedded applications. The past research proposed and evaluated memory banking as a possible ...
CODES
2010
IEEE
13 years 2 months ago
2010
IEEE
In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the perfor...