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HIPC
2000
Springer
10 years 2 months ago
Memory Consistency and Process Coordination for SPARC Multiprocessors
Abstract. Simple and unified non-operational specifications of the three memory consistency models Total Store Ordering (TSO), Partial Store Ordering (PSO), and Relaxed Memory Orde...
Lisa Higham, Jalal Kawash
WDAG
1998
Springer
107views Algorithms» more  WDAG 1998»
10 years 2 months ago
Java: Memory Consistency and Process Coordination
Lisa Higham, Jalal Kawash
ISCA
2007
IEEE
145views Hardware» more  ISCA 2007»
10 years 5 months ago
Mechanisms for store-wait-free multiprocessors
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...
Thomas F. Wenisch, Anastassia Ailamaki, Babak Fals...
HPCA
1999
IEEE
10 years 2 months ago
Using Lamport Clocks to Reason about Relaxed Memory Models
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J....
EDCC
2005
Springer
10 years 4 months ago
Novel Generic Middleware Building Blocks for Dependable Modular Avionics Systems
Abstract. The A3M project aimed to define basic building blocks of a middleware meeting both dependability and real-time requirements for a wide range of space systems and applicat...
Christophe Honvault, Marc Le Roy, Pascal Gula, Jea...
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