87 search results - page 17 / 18 » Memory Management in a Combined VIA SCI Hardware |
GRID
2000
Springer
13 years 8 months ago
2000
Springer
The creation of parameter study suites has recently become a more challenging problem as the parameter studies have become multi-tiered and the computational environment has becom...
SASN
2006
ACM
13 years 11 months ago
2006
ACM
In a large sensor network, in-network data aggregation, i.e., combining partial results at intermediate nodes during message routing, significantly reduces the amount of communic...
HPCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
ISCA
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
DSD
2009
IEEE
14 years 6 hour ago
2009
IEEE
Abstract—Verification of application requirements is becoming a bottleneck in system-on-chip design, as the number of applications grows. Traditionally, the verification comple...