34 search results - page 3 / 7 » Memory Model = Instruction Reordering Store Atomicity |
ISOLA
2010
Springer
13 years 4 months ago
2010
Springer
Abstract. Memory models of shared memory concurrent programs define the values a read of a shared memory location is allowed to see. Such memory models are typically weaker than t...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...
ASPLOS
2006
ACM
13 years 11 months ago
2006
ACM
Visibility is a property of a programming language’s memory model that determines when values stored by one concurrent computation become visible to other computations. Our work...
MICRO
2003
IEEE
13 years 11 months ago
2003
IEEE
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
HPCA
2004
IEEE
14 years 6 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...