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» Memory coherence activity prediction in commercial workloads
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ASPLOS
2009
ACM
14 years 6 months ago
Phantom-BTB: a virtualized branch target buffer design
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
Ioana Burcea, Andreas Moshovos
MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
13 years 11 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
HPCA
2008
IEEE
14 years 6 months ago
EXCES: External caching in energy saving storage systems
Power consumption within the disk-based storage subsystem forms a substantial portion of the overall energy footprint in commodity systems. Researchers have proposed external cach...
Luis Useche, Jorge Guerra, Medha Bhadkamkar, Mauri...
IMC
2009
ACM
14 years 8 days ago
Network level footprints of facebook applications
With over half a billion users, Online Social Networks (OSNs) are the major new applications on the Internet. Little information is available on the network impact of OSNs, althou...
Atif Nazir, Saqib Raza, Dhruv Gupta, Chen-Nee Chua...
SPAA
2006
ACM
13 years 11 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...