254 search results - page 1 / 51 » Memory copies in multi-level memory systems |
ISCA
1998
IEEE
13 years 8 months ago
1998
IEEE
Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval...
CORR
2010
Springer
12 years 11 months ago
2010
Springer
A construction using the E8 lattice and Reed-Solomon codes for error-correction in flash memory is given. Since E8 lattice decoding errors are bursty, a Reed-Solomon code over GF(2...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
We discover significant value-dependent programming energy variations in multi-level cell (MLC) flash memories, and introduce an energy-aware data compression method that minimize...
TVLSI
2010
12 years 11 months ago
2010
By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density ad...
ISCA
2007
IEEE
13 years 4 months ago
2007
IEEE
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...