110 search results - page 1 / 22 » Memory hierarchy exploration for low power architectures in ... |
ICIP
2001
IEEE
14 years 6 months ago
2001
IEEE
PATMOS
2000
Springer
13 years 8 months ago
2000
Springer
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
DAC
1999
ACM
14 years 6 months ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...