Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
Background: Visualization of sequence annotation is a common feature in many bioinformatics tools. For many applications it is desirable to restrict the display of such annotation...
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
BDDs and their algorithms implement a decision procedure for Quanti ed Propositional Logic. BDDs are a kind of acyclic automata. Unrestricted automata (recognizing unbounded string...
vel Meta-Reasoning with Higher-Order Abstract Syntax Alberto Momigliano, Simon Ambler. A Normalisation Result for Higher-Order Calculi with Explicit Substitutions Eduardo Bonelli. ...