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» Metrics for Architecture-Level Lifetime Reliability Analysis
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ISPASS
2008
IEEE
13 years 10 months ago
Metrics for Architecture-Level Lifetime Reliability Analysis
Abstract— This work concerns metrics for evaluating microarchitectural enhancements to improve processor lifetime reliability. A commonly reported reliability metric is mean time...
Pradeep Ramachandran, Sarita V. Adve, Pradip Bose,...
ASAP
2005
IEEE
112views Hardware» more  ASAP 2005»
13 years 10 months ago
On the Advantages of Serial Architectures for Low-Power Reliable Computations
This paper explores low-power reliable microarchitectures for addition. Power, speed, and reliability (both defect- and fault-tolerance) are important metrics of system design, sp...
Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray R...
DAC
2007
ACM
14 years 5 months ago
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhamm...
MICRO
2009
IEEE
144views Hardware» more  MICRO 2009»
13 years 11 months ago
Characterizing flash memory: anomalies, observations, and applications
Despite flash memory’s promise, it suffers from many idiosyncrasies such as limited durability, data integrity problems, and asymmetry in operation granularity. As architects, ...
Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, ...