2 search results - page 1 / 1 » Micro-Network for SoC: Implementation of a 32-Port SPIN netw... |
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a physical imrplementation of a 32-ports SPIN micro-network. For a 0.13 micron CMOS process, the total area is 4.6 ¢£¢¥¤ , for a cumulated bandwidth of about 100 G...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...