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APCSAC
2000
IEEE
11 years 11 months ago
Micro-Threading: A New Approach to Future RISC
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...
Chris R. Jesshope, Bing Luo
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
12 years 1 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
12 years 3 months ago
Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation
Modeling and simulating pipelined processors in procedural languages such as C/C++ requires lots of cost in handling concurrent events, which hinders fast simulation. A number of ...
In-Cheol Park, Se-Hyeon Kang, Yongseok Yi
TVLSI
2008
152views more  TVLSI 2008»
11 years 6 months ago
MMV: A Metamodeling Based Microprocessor Validation Environment
With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validati...
Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Di...
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