41 search results - page 1 / 9 » Microarchitectural Wire Management for Performance and Power... |
HPCA
2005
IEEE
13 years 10 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
MICRO
2012
IEEE
11 years 7 months ago
2012
IEEE
The past 10 years have delivered two significant revolutions. (1) Microprocessor design has been transformed by the limits of chip power, wire latency, and Dennard scaling—leadi...
HPCA
2007
IEEE
14 years 4 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
MICRO
2003
IEEE
13 years 9 months ago
2003
IEEE
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-...
WMPI
2004
ACM
13 years 10 months ago
2004
ACM
Clustered microarchitectures are an effective organization to deal with the problem of wire delays and complexity by partitioning some of the processor resources. The organization ...