63 search results - page 4 / 13 » Microarchitecture and Performance Analysis of Godson-2 SMT P... |
MICRO
1994
IEEE
13 years 10 months ago
1994
IEEE
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
ISPASS
2007
IEEE
14 years 2 days ago
2007
IEEE
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...
ICPP
2008
IEEE
14 years 6 days ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
ISCA
1997
IEEE
13 years 10 months ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...