9 search results - page 1 / 2 » Microarchitecture evaluation with floorplanning and intercon... |
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Conventionally, microarchitecture designs are mainly guided by the maximum throughput (measured as IPC) and fail to evaluate the impact of architectural decisions on the physical ...