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DATE
2009
IEEE
95views Hardware» more  DATE 2009»
13 years 10 months ago
Minimization of NBTI performance degradation using internal node control
—Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for ci...
David R. Bild, Gregory E. Bok, Robert P. Dick
ATS
2009
IEEE
92views Hardware» more  ATS 2009»
13 years 1 months ago
M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay
Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time a...
Song Jin, Yinhe Han, Lei Zhang 0008, Huawei Li, Xi...
DAC
2007
ACM
14 years 4 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
CDC
2009
IEEE
142views Control Systems» more  CDC 2009»
13 years 1 months ago
Asynchronous distributed optimization with minimal communication and connectivity preservation
Abstract-- We consider problems where multiple agents cooperate to control their individual state so as to optimize a common objective while communicating with each other to exchan...
Minyi Zhong, Christos G. Cassandras
NPL
2006
137views more  NPL 2006»
13 years 3 months ago
Minimal Structure of Self-Organizing HCMAC Neural Network Classifier
The authors previously proposed a self-organizing Hierarchical Cerebellar Model Articulation Controller (HCMAC) neural network containing a hierarchical GCMAC neural network and a ...
Chih-Ming Chen, Yung-Feng Lu, Chin-Ming Hong