2 search results - page 1 / 1 » Miss Penalty Reduction Using Bundled Capacity Prefetching in... |
IPPS
2003
IEEE
13 years 10 months ago
2003
IEEE
While prefetch has proven itself useful for reducing cache misses in multiprocessors, traffic is often increased due to extra unused prefetch data. Prefetching in multiprocessors...
MICRO
2007
IEEE
13 years 11 months ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...