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» Miss Rate Prediction across All Program Inputs
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ISCA
2000
IEEE
92views Hardware» more  ISCA 2000»
13 years 9 months ago
Trace preconstruction
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
Quinn Jacobson, James E. Smith
CGO
2004
IEEE
13 years 9 months ago
Static Identification of Delinquent Loads
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...
Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong
IEEEPACT
1998
IEEE
13 years 9 months ago
Static Methods in Hybrid Branch Prediction
Hybrid branch predictors combine the predictions of multiple single-level or two-level branch predictors. The prediction-combining hardware -- the "meta-predictor" -may ...
Dirk Grunwald, Donald C. Lindsay, Benjamin G. Zorn
RTAS
2005
IEEE
13 years 11 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
GECCO
2008
Springer
130views Optimization» more  GECCO 2008»
13 years 6 months ago
VoIP speech quality estimation in a mixed context with genetic programming
Voice over IP (VoIP) speech quality estimation is crucial to providing optimal Quality of Service (QoS). This paper seeks to provide improved speech quality estimation models with...
Adil Raja, R. Muhammad Atif Azad, Colin Flanagan, ...