8 search results - page 2 / 2 » Mitigating the Impact of Process Variations on Processor Reg... |
HPCA
2006
IEEE
14 years 5 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
CASES
2007
ACM
13 years 9 months ago
2007
ACM
The last decade has witnessed the emergence of the Application Specific Instruction-set Processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user...
MICRO
1998
IEEE
13 years 9 months ago
1998
IEEE
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...