Sciweavers

48 search results - page 10 / 10
» Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Powe...
Sort
View
VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
13 years 10 months ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
13 years 9 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
ISLPED
1999
ACM
236views Hardware» more  ISLPED 1999»
13 years 8 months ago
Modeling and automating selection of guarding techniques for datapath elements
While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal ...
William E. Dougherty, Donald E. Thomas