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IPPS
2007
IEEE
13 years 11 months ago
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
Christopher Claus, Florian Helmut Müller, Joh...
DAC
2006
ACM
14 years 5 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
AINA
2007
IEEE
13 years 11 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
ICNP
2006
IEEE
13 years 10 months ago
Benefit-based Data Caching in Ad Hoc Networks
—Data caching can significantly improve the efficiency of information access in a wireless ad hoc network by reducing the access latency and bandwidth usage. However, designing e...
Bin Tang, Himanshu Gupta, Samir R. Das
DEXA
2006
Springer
139views Database» more  DEXA 2006»
13 years 8 months ago
Distributed Continuous Range Query Processing on Moving Objects
Recent work on continuous queries has focused on processing queries in very large, mobile environments. In this paper, we propose a system leveraging the computing capacities of mo...
Haojun Wang, Roger Zimmermann, Wei-Shinn Ku