46 search results - page 2 / 10 » Model Checking for a First-Order Temporal Logic Using Multiw... |
MJ
2006
13 years 4 months ago
2006
In this paper, we describe a hybrid tool for hardware formal verification that links the HOL (higher-order logic) theorem prover and (multiway decision graphs) model checker. Our ...
ISMVL
2010
IEEE
13 years 10 months ago
2010
IEEE
—Multiway Decision Graphs (MDGs) subsume Binary Decision Diagrams (BDDs) and extend them by a first-order formulae suitable for model checking of data path circuits. In this pap...
ATVA
2004
Springer
13 years 8 months ago
2004
Springer
While model checking suffers from the state space explosion problem, theorem proving is quite tedious and impractical for verifying complex designs. In this work, we present a veri...
FMCAD
1998
Springer
13 years 9 months ago
1998
Springer
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
FM
2003
Springer
13 years 10 months ago
2003
Springer
We present a novel application on model checking through SPIN as a means for verifying purely descriptive specifications written in TRIO, a first order, linear-time temporal logic ...