Formal verification is an important issue in circuit and system design. In this context, Bounded Model Checking (BMC) is one of the most successful techniques. But even if all sp...
Metamodels are functions with calibrated parameters, used actions and simplifications of the simulation model. A metamodel exposes the system’s input-output relationship and ca...
Abstract. In recent years a bundle of parallel and distributed algorithms for verification of finite state systems has appeared. We survey distributed-memory enumerative LTL mode...
This paper presents a case study in modelling and verifying the Linux Virtual File System (VFS). Our work is set in the context of Hoare’s verification grand challenge and, in p...
The interplay back and forth between software model checking and hardware model checking has been fruitful for both. Originally intended for the analysis of concurrent software, mo...
Edmund M. Clarke, Anubhav Gupta, Himanshu Jain, He...