Sciweavers

160 search results - page 1 / 32
» Modeling, specification, and verification of automaton progr...
Sort
View
PCS
2008
45views more  PCS 2008»
13 years 5 months ago
Modeling, specification, and verification of automaton programs
E. V. Kuzmin, Valery A. Sokolov
ECRTS
1999
IEEE
13 years 10 months ago
Timed automaton models for simple programmable logic controllers
We give timed automaton models for a class of Programmable Logic Controller (PLC) applications, that are programmed in a simple fragment of the language Instruction Lists as defin...
Angelika Mader, Hanno Wupper
CORR
2010
Springer
176views Education» more  CORR 2010»
13 years 5 months ago
Bus Protocols: MSC-Based Specifications and Translation into Program of Verification Tool for Formal Verification
Message Sequence Charts (MSCs) are an appealing visual formalism mainly used in the early stages of system design to capture the system requirements. However, if we move towards a...
Kamrul Hasan Talukder
FORMATS
2004
Springer
13 years 9 months ago
Decomposing Verification of Timed I/O Automata
This paper presents assume-guarantee style substitutivity results for the recently published timed I/O automaton modeling framework. These results are useful for decomposing verifi...
Dilsun Kirli Kaynar, Nancy A. Lynch
RE
2001
Springer
13 years 10 months ago
Events and Constraints: A Graphical Editor for Capturing Logic Requirements of Programs
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
Margaret H. Smith, Gerard J. Holzmann, Kousha Etes...