59 search results - page 12 / 12 » Modeling Cache Effects at the Transaction Level |
IPPS
2008
IEEE
13 years 11 months ago
2008
IEEE
The advent of multicore processors requires mainstream concurrent programming languages with high level concurrency constructs and effective debugging techniques. Unfortunately, m...
APCSAC
2004
IEEE
13 years 8 months ago
2004
IEEE
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory. This paper is a first look at the value of RAMpage to ...
ISPASS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...
SIGMOD
2009
ACM
14 years 5 months ago
2009
ACM
The past few decades have witnessed a chronic and widening imbalance among processor bandwidth, disk capacity, and access speed of disk. According to Amdhal's law, the perfor...