59 search results - page 4 / 12 » Modeling Cache Effects at the Transaction Level |
ICSEA
2007
IEEE
14 years 2 days ago
2007
IEEE
— This paper demonstrates that the algorithmic performance of end user programs may be greatly affected by the two or three level caching scheme of the processor, and we introduc...
ICDE
2006
IEEE
14 years 7 months ago
2006
IEEE
Scheduling/prioritization of DBMS transactions is important for many applications that rely on database backends. A convenient way to achieve scheduling is to limit the number of ...
IPPS
2005
IEEE
13 years 11 months ago
2005
IEEE
With the latest high-end computing nodes combining shared-memory multiprocessing with hardware multithreading, new scheduling policies are necessary for workloads consisting of mu...
FMCAD
2007
Springer
13 years 9 months ago
2007
Springer
Modeling hardware through atomic guard/action transitions with interleaving semantics is popular, owing to the conceptual clarity of modeling and verifying the high level behavior ...
WSC
2000
13 years 7 months ago
2000
We discuss some of the difficulties present in trace collection and trace-driven cache simulation. We then describe our multiprocessor tracing technique and verify that it accurat...