221 search results - page 2 / 45 » Modeling Interconnect Variability Using Efficient Parametric... |
CDC
2009
IEEE
13 years 8 months ago
2009
IEEE
Abstract-- Many model order reduction methods for parameterized systems need to construct a projection matrix V which requires computing several moment matrices of the parameterize...
VLSI
2007
Springer
13 years 11 months ago
2007
Springer
Abstract—Analysis and verification environments for nextgeneration nano-scale RFIC designs must be able to cope with increasing design complexity and to account for new effects,...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
The relative tolerances for interconnect and device parameter variations have not scaled with feature sizes which have brought about significant performance variability. As we sca...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we propose a novel parameterized interconnect order reduction algorithm, CORE, to efficiently capture both inter-die and intra-die variations. CORE applies a two-ste...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
As process technology continues to scale into the nanoscale regime, interconnect plays an ever increasing role in determining VLSI system performance. As the complexity of these sy...