71 search results - page 2 / 15 » Modeling and Simulating Memory Hierarchies in a Platform-Bas... |
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
CGO
2003
IEEE
13 years 8 months ago
2003
IEEE
In this paper, we present METRIC, an environment for determining memory inefficiencies by examining data traces. METRIC is designed to alter the performance behavior of applicatio...
SBACPAD
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...
ISCA
1997
IEEE
13 years 8 months ago
1997
IEEE
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
GLVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...