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» Modeling and minimization of PMOS NBTI effect for robust nan...
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DAC
2006
ACM
10 years 4 months ago
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the deg...
Rakesh Vattikonda, Wenping Wang, Yu Cao
ISQED
2006
IEEE
259views Hardware» more  ISQED 2006»
10 years 4 months ago
Impact of NBTI on SRAM Read Stability and Design for Reliability
— Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious ...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
ISQED
2010
IEEE
177views Hardware» more  ISQED 2010»
10 years 5 months ago
Multi-corner, energy-delay optimized, NBTI-aware flip-flop design
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
Hamed Abrishami, Safar Hatami, Massoud Pedram
TVLSI
2008
176views more  TVLSI 2008»
9 years 10 months ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
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