9 search results - page 2 / 2 » Modeling the Overshooting Effect for CMOS Inverter in Nanome... |
DSN
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
: While delay modeling of gates with a single switching input has received considerable attention, the case of multiple inputs switching in close temporal proximity is just beginni...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
As CMOS technology scales into the nanometer regime, power dissipation and associated thermal concerns in high-performance ICs due to on-chip hot-spots and thermal gradients are b...
DAC
1998
ACM
14 years 6 months ago
1998
ACM
- A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicromete...