327 search results - page 2 / 66 » Modelling and Evaluation of a Network on Chip Architecture U... |
IEEEHPCS
2010
13 years 3 months ago
2010
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...
IJCNN
2000
IEEE
13 years 9 months ago
2000
IEEE
: Conventional hardware platforms are far from reaching real-time simulation requirements of complex spiking neural networks (SNN). Therefore we designed an accelerator board with ...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
DAC
2010
ACM
13 years 6 months ago
2010
ACM
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...
MMB
2001
Springer
13 years 9 months ago
2001
Springer
This paper provides a performance evaluation of the TETRAPOL random access protocol. The results are based on a Markovian model which is also presented. The Markovian model is use...